1. Field of the Invention
The present invention relates to a programmable counter circuit which has its operable frequency improved.
2. Description of the Prior Art
A programmable counter which operates as an N-step counter having a variable frequency dividing ratio N, is composed of a counter circuit comprising a multistage connection of flip-flops and a loading circuit for inputting an initial value (N) into the counter circuit. FIG. 1 shows an example of a conventional programmable counter circuit indicated generally by CNT, in which a plurality of stages of flip-flops P.sub.D1, P.sub.D2, . . . are cascade-connected. The flip-flop P.sub.D1 of the first stage is supplied with a clock signal F.sub.IN. The flip-flops P.sub.D2, P.sub.D3, . . . of the following stages are each supplied with the output from the immediately preceding stage and bits DL.sub.1, DL.sub.2, DL.sub.3, . . . forming initial values are respectively loaded into the respective flip-flops of the individual stages. The bits DL.sub.1, DL.sub.2, DL.sub.3, . . . are bits of binary numbers and representing the numeric values of the first, second, fourth, eighth, . . . digits in sequential order. For loading the initial values DL.sub.1, DL.sub.2, . . . in the counter circuit CNT, the numeric values of the bits DL.sub.1, DL.sub.2, . . . are first determined by setting digital switches or latch circuits and then a load signal LOAD is applied to a common line L.sub.1, by which the numeric values DL.sub.1, DL.sub.2, . . . are respectively loaded into the flip-flops P.sub.D1, P.sub.D2, . . . . The clock counting of the flip-flops is down-counting. Assuming, for example, that the initial values DL.sub.1, DL.sub.2, . . . are "000100 . . . ",that is "8" in the decimal notation, an "8" count is counted by loading 8 into the counter and counting down to 7, 6, . . . by the down-counting of the clock signal F.sub.IN and when the count value reaches "0", "8" has been counted by the counter; thus, in this case, the counter serves as an 8-step counter. By setting the initial value to "20" with the bits DL.sub.1, DL.sub.2, . . . set to "0010100 . . . " and performing the counting as mentioned above, the counter functions as a 20-step counter. In this way, a desired counter can be formed.
Basically a load signal generator may be one that generates the load signal LOAD when the count value of the counter circuit CNT becomes zero. When the counter circuit CNT is counted down to "0" and it is detected by a gate circuit that outputs Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.12 of the flip-flops P.sub.D1, P.sub.D2, P.sub.D3, . . . P.sub.D12 are all "0", the detected output is directly used as the load signal LOAD. When the initial value bits DL.sub.1, DL.sub.2, . . . are loaded into some of the flip-flops P.sub.D1, P.sub.D2, . . . by the load signal, the above-mentioned condition required for load signal generation is immediately removed. Note, there is a slight time lag in the loading of the bits to the respective flip-flops. Thus, the load signal LOAD disappears, so that the initial values can no longer be loaded into the remaining flip-flops. To improve this above-mentioned system, it is common practice in the art to employ a signal generator LDG such as shown in FIG. 3 which is commonly referred to as an early decoder or look ahead circuit. This look ahead circuit comprises a specific count value detector circuit DET comprising NOR gates NOR.sub.1 to NOR.sub.4 and NAND gates NAND.sub.1 to NAND.sub.4 and a shift register SHR comprising D flip-flops DFF.sub.1 to DFF.sub.3. The detector circuit DET is one in which a Q or Q output from the counter circuit CNT is selectively applied to each gate to derive from NAND gate NAND.sub.4 of the last stage the following output H : EQU H =Q.sub.1 +Q.sub.2 +Q.sub.3 +Q.sub.4 + . . . +Q.sub.12.
Accordingly, in the detector DET of this example the output H is "0" when Q.sub.1 =Q.sub.2 =Q.sub.4 = . . . =Q.sub.12 =0 and Q.sub.3 =1, that is, when the counter value is "4". The output H =0 is applied as a detection signal of the specific count value "4" to the shift register SHR. The shift register SHR inputs therein the output from the gate NAND.sub.4, using the same clock signal F.sub.IN as the counter circuit CNT, and then after having shifted for three clock signals and, accordingly when the count value of the counter circuit CNT has reached "1", the shift register SHR generates the load signal LOAD. With this system, each flip-flop is initialized by the load signal and even if the output from the NAND gate NAND.sub.4 is made H =1 by the initialization, since it is the shift register SHR that outputs the load signal and since the shift register SHR does not change its state for at least one clock signal, the load signal will not disappear within one clock period; thus, the load signal is produced until the count value "0" is reached.
In such a programmable counter, as its operating frequency is raised, the load circuit cannot keep up with the increase in the operating fequency even though each flip-flop is still operable, presenting the problem that the highest operating frequency is limited. In other words, as the number of stages of flip-flops increases, the load signal line L.sub.1 becomes longer; especially in a MOS circuit, the capacitance of the signal line L.sub.1 increases and rounds the waveform of the load signal transmitted over the signal line L.sub.1, introducing the possibility of an erroneous operation.
The rounding of the waveform can be avoided by applying the load signal to a waveform shaping circuit. The circuit arrangement therefor is shown in FIG. 2. In the illustrated example, a buffer BUF formed by a series connection of two inverters is shown to be inserted between load terminals of every other flip-flop. With such an arrangement, the load signal is applied only to the first stage flip-flop P.sub.D1 and the buffer BUF connected thereto and each of the other buffers drives the flip-flop of the succeeding stage and the buffer connected thereto, so that the load on the load signal generator LDG is greatly alleviated and the rounding of the waveform is removed by each buffer and hence does not become critical. With this arrangement, however, a delay in signal propagation by each buffer is accumulated producing a large delay in the signal propagation of the signal arriving at the terminating flip-flop and, as a result, it is likely that a plurality of load signals occur, making the loading inaccurate. Accordingly, in the circuit of FIG. 2 the highest operating frequency depends on the delay of the load circuit; therefore, an extensive improvement cannot be expected of this circuit though it slightly improves on the circuit of FIG. 1. This will hereinbelow be further described with reference to FIGS. 4 and 5.
FIG. 4 is a waveform diagram depicting the operation of the programmable counter shown in FIG. 2. In FIG. 4, DL.sub.3 =DL.sub.6 =1 and the other bits are "0"; that is, the initial value is "36". Assuming that the level of the output H =0 from the gate NAND.sub.4 is produced upon occurrence of a second clock signal F.sub.IN in FIG. 2, a low-level load signal is generated after the occurrence of three clock signals and the initial values DL.sub.1, DL.sub.2, . . . are loaded into the flip-flops P.sub.D1, P.sub.D2, . . . in a sequential order while being delayed by a signal propagation delay time .tau..sub.1. By the loading of the initial value DL.sub.1, the flip-flop P.sub.D1 is returned to the low level although it is to be high-level, and the NAND gate NAND.sub.4 provides an output H.sub.2 having a low-level other than its original output H.sub.1. The high-level of H is immediately restored by the lowering of the output G down to the low level, as indicated by G.sub.1, so that the loading does not take place twice. Thus, in the case where the initial value is not a certain special value, normal operation is maintained even if the operating frequency is a little high. When loading an initial value such that DL.sub.3 =1 and a high-order bit becomes "1" as indicated by Q.sub.12 in FIG. 5, however, while the loading signal is transmitted to the flip-flop P.sub.D12, "1" is loaded into the flip-flop P.sub.D3 and there can occur the state in which the outputs from the remaining flip-flops are "0". Since this means a count value "4", the NAND gate NAND.sub.4 yields a low-level output H.sub.2 and after three clock signals the shift register SHR produces a load signal LOAD'.